CPU3680 MOTOROLA 处理器模块

CPU3680 MOTOROLA 处理器模块
采用内置低功耗平台的ARM?处理器(600MHz、T.I. Cortex-A8)的SoC 「AM3354」，在确保足够执行能力的同时，实现了低消费电力。
减轻维护保全业务的无风扇设计
废除CPU风扇、存储器采用SD卡、完全无转动机构设计。另外，使用产品附带的防水垫圈、防水螺钉设置时，前端部分防止粉尘或异物侵入，能够满足IP65标准的防水规格。极力减少易老化零部件的使用，大幅度减轻了维护保全业务的负担。
节省空间的设计，贡献于装置的小型化
采用5.7英寸LCD的小型、轻量[大约0.8kg]的触摸屏一体型PC机。贡献于装置的小型化。还可利用VESA规格100×100mm标准的安装结构，安置在LCD支架。

CPU3680

配置USB、LAN等计算机的标准扩展接口
配置了USB×1、100BASE-T×1、RS-232C×1等接口机能。同时附带各个接口的驱动软件。
CPU3680 MOTOROLA 处理器模块
附带支持系统开发的软件工具“CONTEC Manager”
配置了FTP服务器机能、时间表功能、利用NTP的自动时间调整机能、Auto RUN机能等，有助于构件系统的软件工具“CONTEC Manager”。
CPU3680 MOTOROLA 处理器模块整个系统工作流程可以简单描述如下：系统上电后，首先DSP由flash实现自举，并运行引导程序，之后转入EDMA等待状态，FPGA初始化后等待外部图像采集命令，收到图像采集命令后开始进行图像采集，并对采集到的图像进行预处理，预处理后的图像经过FIFO缓冲，在存储一定量的数据之后，FPGA通过半满信号向DSP发送EDMA请求，等待DSP响应，DSP一旦收到来自FPGA的EDMA请求，立即建立EDMA通道，从FIFO中读取数据到L2存储器，存满一帧图像后DSP开始图像压缩，等待一幅图像压缩完成之后，DSP会向FPGA发送中断信号，FPGA在收到中断信号后开始从 FIFO中读取压缩后的图像数据。一帧数据读完后，判断编码信号是否有效，如果有效则按同样的规则对下一帧图像进行压缩，如果无效则通知DSP结束。

CPU3680

CPU3680 MOTOROLA Processor module
ARM with a built-in low-power platform? The SoC “AM3354” with a 600MHz processor (T.I. Cortex-A8) achieves low power consumption while ensuring sufficient execution capacity.
A fanless design that eases maintenance security
The CPU fan is abolished, the memory is SD card, and there is no rotating mechanism design. In addition, when using the waterproof washer and waterproof screw attached to the product, the front part prevents dust or foreign body intrusion, and can meet the waterproof specifications of IP65 standard. Minimize the use of easily aged parts, greatly reducing the burden of maintenance and security business.
The space-saving design contributes to the miniaturization of the device
Small, lightweight [approximately 0.8kg] touchscreen one-body PC with a 5.7 inch LCD. Contribute to the miniaturization of the device. It can also be installed in the LCD bracket with VESA standard 100×100mm mounting structure.
Standard extension interfaces for computers such as USB and LAN are configured
USB×1, 100BASE-T×1, RS-232C×1 and other interface functions are configured. At the same time, the driver software of each interface is attached.
CPU3680 MOTOROLA Processor module
Includes software tool “CONTEC Manager” to support system development
CONTEC Manager, a software tool for building the system, is equipped with FTP server function, schedule function, automatic time adjustment function using NTP, Auto RUN function, etc.
CPU3680 MOTOROLA Processor Module The entire system workflow can be simply described as follows: After the system is powered on, the DSP is bootstrapped by flash first, and the boot program is run, and then it is transferred to the EDMA waiting state. After initialization, the FPGA waits for the external image acquisition command. After receiving the image acquisition command, the image acquisition begins, and the acquired image is preprocessed. After storing a certain amount of data, FPGA sends EDMA request to DSP through half-full signal, waiting for DSP response. Once DSP receives EDMA request from FPGA, it immediately establishes EDMA channel, reads data from FIFO to L2 memory, and starts image compression after storing one frame of image. After an image compression is completed, the DSP sends an interrupt signal to the FPGA, and the FPGA begins to read the compressed image data from the FIFO after receiving the interrupt signal. After reading a frame of data, the encoded signal is judged whether it is valid. If it is valid, the next frame image is compressed according to the same rules. If it is invalid, the DSP is notified to end.

CPU3680